From the human body, the environment and internal electronic equipment for semiconductor chip precision electrostatic will cause damage, such as through the components inside the thin insulating layer; a gate MOSFET lesion and CMOS components; CMOS device triggers lock; short PN junction reverse biased; short road to biased PN junction; active devices within the melting welding wire or wire. In order to eliminate the electrostatic discharge (ESD) interference and damage to the electronic equipment, need to take a variety of technical means of prevention.
In the design of PCB board, can be layered, proper layout and installation of anti ESD design and implementation of PCB. In the design process, through the forecast can be modified only to increase or decrease the vast majority of design components. By adjusting the PCB layout, can be very good to prevent ESD. The following are some of the common measure.
* multilayer PCB is used as far as possible, the double PCB, the ground plane and power plane, and closely spaced signal earth line spacing can reduce common mode impedance and inductance coupling, so as to achieve the double PCB 1/10 to 1/100. As each signal layer are close to a power supply layer or ground layer. For the top and bottom surfaces are components, with a short connecting wire and a lot of filling high density PCB, can consider to use the inner line.
* for a double PCB, by closely interwoven power and ground grid. Power line is close to the ground, between vertical and horizontal line or fill area, as much as possible to connect. The size of the grid side is less than or equal to 60mm, if possible, the grid size should be less than 13mm.
* make sure that every circuit as compact as possible.
As far as possible to all connectors are put aside.
If possible, the introduction of the power line from the card and away from the central, to be directly influenced by ESD region.